Implementation of High Reliable 6T SRAM Cell Design
نویسندگان
چکیده
Memory can be formed with the integration of large number of basic storing element called cells. SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit. Modified read and write circuits were proposed in this paper to address incorrect read and write operations in conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are carried out using MENTOR GRAPHICS.
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